1. Technical Field
Various embodiments generally relate to a semiconductor device and a driving method thereof, and more particularly, to a technology related to a semiconductor device including an error correction code circuit.
2. Related Art
As a voltage applied to a memory cell is lowered and a cell size is reduced, deterioration of soft error tolerance has been problematic. As a semiconductor integrated device using an error correction code (hereinafter, referred to as an ‘ECC’) circuit that corrects such a data error, a circuit technology for correcting failed bits by adding a parity bit to normal data has been disclosed.
That is, after a semiconductor memory device is fabricated, a test is performed to select failed memory cells. According to one of the methods for improving a yield of a semiconductor memory device, an ECC function is provided to the semiconductor memory device.
Such an ECC circuit may be defined as a circuit that performs a function of detecting and correcting defects of data in realtime, and normally adds an additional parity bit to DQ data in DQ data transmission of a memory. That is, the semiconductor memory device checks whether the DQ data and the added parity bit are transmitted according to a prescribed protocol, thereby detecting a data error.
In an on-die ECC circuit, an ECC area is assigned in order to perform an ECC operation in correspondence to all cell arrays. Therefore, as the size of a data area increases, the size of the ECC area also increases, resulting in an increase in the area of a parity area for storing a parity bit.